This paper presents the design of a low-dropout voltage regulator which has a low area and power consumption, as well as an improved transient response. The area reduction is achieved by biasing the power transistor in the triode region. In addition, a dynamic bias network is used in order to reduce its settling time to 300ns for any change in the load current from 100µA to 100mA. The regulator is designed in a Silterra 0.18µm standard CMOS technology and brings a regulated output voltage of 1.8V. All the circuit is biased with 2.3µA only at loads smaller than 1mA, and can recover within 0.3µs for maximum load and input voltage changes. Moreover, the regulator does not need any external capacitor to guarantee its stability