This article presents the description of a Turbo decoder with MAP algorithm in an FPGA using VHDL. The main objetive is related with achieving the algorithm synthesis in terms of logic density and processing speed and with this, show the decoder’s response to the variations of two basics parameters as the number of decoding iterations and the size of the data frames.The options of the MAP algorithm have been analysed and the results of the synthesis obtained with Quartus II are exposed as well as the performance curves of the decoder under the influence of Additive White Gaussian Noise. Finally, the conclusions and recommendations derived from the project are enunciated.