This paper presents an offset voltage correction technique for high-speed digital interfaces. Contrary to conventional way of measuring offset, the proposed technique is based on the phase measurement of a slicer output avoiding the input connection to a common mode voltage. A fully-digital implementation allows phase measurement maintaining offset accuracy. Proper operation of calibration technique is achieved when the input signal is comparable to the offset and sensitivity of the whole interface. Thus, the proposed method could be used during on-line operation, without breaking the communication link. The circuit has been implemented in a 130nm TSMC standard CMOS process, and simulation results show an offset reduction nearly 90% in the analog front-end with a low area overhead.