This work presents the design of a Low-Jitter Ring-VCO-Based single-loop type-I phase-locked loop (PLL) in 180 nm CMOS technology. To increase the phase detector (PD) gain and the margin phase of the PLL, a novel switched capacitor stage inside the Master-Slave Sampling loop filter is proposed. Furthermore, it allows reducing significantly the phase noise (PN) of the ring Voltage-Controlled Oscillator (VCO). Also, a simple and less phase noise PD topology is discussed and compared to the typical XOR gate. From a 50-MHz reference input, a bandwidth of 25-MHz was obtained, leading to a simulated in-band PN of -118 dBc/Hz at 1-MHz offset, 486 fs of integrated jitter and spur level of -63 dB at 1.65 GHz for 10 mW of power consumption and 0.0099 mm 2 of core area.