Automatic standard cell layout generation employs algorithms for transistor folding, placing, and routing. Reported standard transistor placement algorithms neglect to consider, in advance, the full netlist and the routing to generate clean layouts. Here, we introduce a placement algorithm with an optimization for complete routing and pre-layout algorithm awareness. The algorithm applies pseudo-boolean satisfiability to determine the minimum-width transistors in the cell. Placement optimization provides route-awareness to circumvent routing congestion according to pins location. The proposed algorithm is implemented in a full automatic standard cell generation procedure, fulfilling a commercial 180nm technology node design rules. Final generated layouts are 30% more routable than the base SAT formulations, enabling 100% routing in complex cells.