Agile hardware design strategies have shown a fast adoption in academia and industry by bringing ideas from the software development side. However, adopted design methodologies exhibit traditional verification scenarios based on handmade testbenches. Here we describe a verification methodology for RISC-V-based processors with human-independent testbenches creation, employing high-effort verification methods throughout all processor design cycle. We demonstrated the methodology by performing verification tests in a single-issue in-order (SIIO) 32-bit RISC-V ISA based processor described in Chisel. In contrast to standard verification methods, the proposed methodology can detect bugs hard to isolate even after final FPGA implementations in-field. The generated test programs show higher coverage metrics, and χ 30 fewer instructions compared to official RISC-V torture unit tests.