Multi-protocol support applications and complex systems-on-chip demand several clock sources to fulfill the diverse data exchanging. This paper presents an f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> / f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> =3D 15000 tuning range feed-forward differential ring oscillator to reduce the total number of required clock references with no additional frequency dividers. Secondary feed-forward loops allow the oscillator to increase 3X the maximum oscillation frequency up to 1.5GHz while achieving a 100kHz minimum frequency. The proposed feed-forward oscillator generates a kHz-to-GHz output frequency occupying an area of 0.05mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in a pure digital 180nm CMOS process node. Post-layout simulations report an RMS jitter of 3.1ps@1.25GHz with a maximum 8mW@1.5GHz power consumption and a phase error of 1.4°@1.5GHz.