The estimation of performance metrics of a Network-on-Chip (NoC) is an increasingly important aspect of Multiprocessor System-on-Chip (MPSoC) design. As systems grow in number of components and features, the correct design of the Network-on-Chip has a central role in meeting the performance requirements of the system, because it is responsible for the efficient movement of data inside the MPSoC. In this paper a software tool called NoCSimulator which is based in queueing theory for the estimation of latency and throughput of a NoC is proposed. The contribution of this tool is its ability to generate stochastic traffic patterns based on real data traffic of scientific applications, not only synthetic traffic as similar tools reported in literature. This makes it possible to study NoC performance under real working conditions, which gives better insights about NoC behavior, and improves the design space exploration at early stages of system development. NoCSimulator was validated using two state-of-the-art cycle-accurate simulators (BookSim and Garnet). NoCSimulator, based in queueing theory, does not model hardware aspects of the NoC as a cycle-accurate simulator, so, long simulation times of complex systems can be avoided during design space exploration.