Nowadays, an SoC integrates a large number of modules within a single die, which requires implementing a robust communication system to link the whole chip. Buses are a convenient solution for connection of modules, arbitrating communication, timing, and transferring information along the SoC. Although the bus is an essential component in SoC applications, there is a lack of accurate literature about the topic. This brief spotlights the energy issues related to inefficient communication between a master and a time-constrained peripheral in standard bus approaches. Here we introduce an alternative bus protocol to allow direct communication among masters and slaves linked to the peripheral and system domains in low-energy applications. As a result of implementing the proposed bus within an SoC, we present a 5X clock cycle reduction for multiple transactions when compared to TileLink and AHB-Lite/APB approaches.