Spin-Transfer-Torque Magnetic RAM (STT-MRAM) is a promising memory technology due to its ultra-integration density capability; nanosecond read and write operation speeds and CMOS/FinFET fabrication process compatibility. As every silicon technology, STT-MRAMs may be affected by fabrication defects, which may be difficult to detect under process variability in deeply scaled transistor technology. This paper proposes a Design-For-Test (DFT) circuit to detect short defects in the STT-MRAM cells. The proposed methodology is based on the observation that a short defect makes different the amplitude of the current entering and leaving the memory cell. The proposed DFT circuitry is robust to process-induced parameters variations in the memory cell. In such way, defects detection probabilities are increased, and a high-quality product can be guaranteed.