This paper presents a low-cost technique to reduce offset voltage of a dynamic comparator. The proposed method is based on output-data phase measuring. A full-digital implementation is used to measure phase without impacting offset accuracy. Simulation and measured results show that the eye-diagram at the compartor input can be shifted up to 245mV due to offset, achieving a successful correction, and making the technique suitable for high-speed applications. The technique requires less than 500ns to achieve convergence and calibration. In this way, there is not need to break the communication link associated to the comparator. The circuit has been implemented in a 130nm TSMC standard CMOS process and detailed experimental results are shown along this document.