This paper describes a low-cost and low-complexity alternative to reduce the occurrence of Row-Hammer attacks. The detection of an undesired attack is based on the use of an additional memory cell - called dummy cell -, with a larger leakage current and thus a higher sensitivity to crosstalk and coupling noise. This characteristic is achieved due to the use of a wider pass transistor and a smaller storage capacitor. One of the most relevant aspects of this solution is the involved additional low-complexity hardware, occupying less than 0.1% of the whole memory. In addition, the dummy cells can be distributed across the whole memory to hinder hackers identification. Simulations on a 65nm CMOS process were done in order to validate the proposed alternative. Process variations for coupling and interconnections were taken into account in a 64×64 memory array, so that the results keep congruence with a memory dedicate, state-of-art, 28nm process.