In this paper is proposed a methodology for designing a CMOS class-E PA used to drive an inductive link. In order to satisfy the operating conditions imposed by the PA specifications and the available technology, a differential class-E PA with split slab inductor and high level of integration was both designed and simulated. The proposed methodology uses the analytical solution of the ideal class-E PA equations as the first point of an iterative procedure for solving the optimization of the PA. Further, the proposed design set solve the trade-off between ON-resistance and gate capacitance of the switches, resulting in the optimal choice of the power transistors width for a class-E PA with finite DC-feed inductance. In the post-layout simulation, the PAE of the PA was 45.7% when 20.7 dBm.