A Huffman coding scheme with 3.9 compression ratio for the Large Hadron Collider experiment is proposed. A fully-synthesized scheme draws a small footprint layout of 60μm × 60μm in 65nm and 105μm × 105μm in 130nm CMOS process. The maximum operation frequencies are 435MHz for 65nm and 333MHz for 130nm, whereas the power consumption is 1.2mW and 1.9mW respectively. The resulting scheme enables a front-end electronics without any loss of data.
