This work presents the hardware implementation of four hardware profile stream ciphers from the eSTREAM project. The hardware architectures are implemented using structural VHDL and, taking into account the simulation results, the best algorithm for hardware implementation is Trivium, with an 80-bit security level. This implementation requires 8 ALUTs, 289 registers, has a maximum frequency of 915.75 MHz and a throughput of 915 Mbps. The second is Grain-128, followed by Mickey-128 and Decim-128, which have a 128-bit security level. The designs were synthesized on the Altera FPGA Stratix III EP3SE50F484C2.