The effect of orientation of patterns, made in poly and nitride layers deposited and defined over (100) silicon wafers, on dislocation generation during IC processing was investigated. By changing the pattern edges from the <110> to the <100> direction, the probability of dislocation generation was reduced. This can be explained by the orientation of stress raisers out of the {111} slip plane. As a result of defect reduction, the yields of CMOS and CCD circuits was improved.