Abstract In this paper, a device‐level bias‐adaptation technique for improving the linearity‐efficiency trade‐off in Class‐B FET power amplifiers is introduced. The proposed approach uses the low‐current large‐signal intermodulation distortion sweet spot that appears below the V GS pinch‐off voltage as the bias point. A detailed characterization of the sweet‐spot evolution shows that a dynamic dual‐bias adjustment could guarantee, under strong input‐power level variations, low in‐band intermodulation distortion while the amplifier remains working around its highest efficiency value. The proposed technique is validated using an IS‐95 QPSK signal. © 2004 Wiley Periodicals, Inc. Microwave Opt Technol Lett 41: 327–331, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.20132